In classical bus-based architectures, communications between on-chip cores use a blocking protocol. Specifically, while a transfer is underway between an initiator and a target, the bus resources are not available for any other transfers to occur.
Some on-chip interconnect architectures incorporate the use of pipelined polling protocol that alleviates the main inadequacy of a blocking protocol, yet still losing efficiency when communicating with targets with high and unpredictable latency.
For example, when an Intellectual Property (IP) core issues a read request to an on-chip SRAM device with predictable short latency, the response may be guaranteed to become available on the bus during the first attempt by the initiator to accept it. When an IP core issues a read request to an off-chip DRAM device with unpredictable and often high latency, multiple accesses to the bus may be required before the response becomes available to be accepted by the requesting entity. Each such access to the bus results in wasted cycles that ultimately degrade the overall bandwidth and efficiency of the system.